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M390S5658MT1
M390S5658MT1 SDRAM DIMM
Preliminary PC133 Registered DIMM
256Mx72 SDRAM DIMM with PLL & Register based on Stacked 256Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
GENERAL DESCRIPTION
The Samsung M390S5658MT1 is a 256M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M390S5658MT1 consists of eighteen CMOS Stacked 256Mx4 bit Synchronous DRAMs in two TSOP-II 400mil packages, three 18-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package for clock and one 2K EEPROM in 8pin TSSOP package for Serial Presence Detect on a 168-pin glass-epoxy substrate. Two 0.22uF and one 0.0022uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M390S5658MT1 is a Dual Inline Memory Module and is intented for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Part No. M390S5658MT1-C75 * * * * * Max Freq. (Speed) 133MHz (7.5ns @ CL=3)
Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin Front Pin Front DQ18 DQ19 VDD DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS *CLK2 NC *WP **SDA **SCL VDD Pin Back Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin Back 29 DQM1 57 58 CS0 30 59 31 DU 60 32 VSS 61 33 A0 62 34 A2 63 35 A4 64 36 A6 65 37 A8 38 A10/AP 66 67 39 BA1 68 40 VDD 69 41 VDD 42 CLK0 70 71 43 VSS 44 DU 72 73 45 CS2 46 DQM2 74 47 DQM3 75 76 48 DU 77 49 VDD 78 50 NC 79 51 NC 80 52 CB2 81 53 CB3 82 54 VSS 55 DQ16 83 56 DQ17 84 VSS 85 86 DQ32 87 DQ33 88 DQ34 89 DQ35 VDD 90 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 96 VSS 97 DQ41 98 DQ42 99 DQ43 100 DQ44 101 DQ45 102 VDD 103 DQ46 104 DQ47 105 CB4 106 CB5 107 VSS 108 NC NC 109 110 VDD 111 CAS 112 DQM4 141 DQ50 142 DQ51 143 VDD 144 DQ52 NC 145 146 *VREF 147 REGE VSS 148 149 DQ53 150 DQ54 151 DQ55 VSS 152 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VDD 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 *CLK3 NC 164 165 **SA0 166 **SA1 167 **SA2 168 VDD
PIN NAMES
Pin Name A0 ~ A13 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 CKE0 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF REGE SDA SCL SA0 ~ 2 DU NC *WP Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection Write protection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
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M390S5658MT1
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
Preliminary PC133 Registered DIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA13, Column address : CA0 ~ CA9, CA11,CA12 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A13 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask
REGE
Register enable
DQ0 ~ 63 CB0 ~ 7 VDD/VSS
Data input/output Check bit Power supply/ground
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M390S5658MT1
FUNCTIONAL BLOCK DIAGRAM
BCS1,B2CKE0 BCS0,B0CKE0 PCLK0 B0RAS,B0CAS,B0WE,B0BA0,B0BA1 B0A0~B0A12 BDQM0 DQ0~3 10 PCLK1 CLK CS1,CKE D0L CTL Add DQM DQ0~3 CLK CS1,CKE D1L CTL Add DQM DQ0~3 CLK CS1,CKE D2L CTL Add DQM DQ0~3 CLK CS1,CKE D3L CTL Add DQM DQ0~3 CLK CS1,CKE D4L CTL Add DQM DQ0~3 CLK CS0,CKE D0U CTL Add DQM DQ0~3 CLK CS0,CKE D1U CTL Add DQM DQ0~3 CLK CS0,CKE D2U CTL Add DQM DQ0~3 CLK CS0,CKE D3U CTL Add DQM DQ0~3 CLK CS0,CKE D4U CTL Add DQM DQ0~3
Preliminary PC133 Registered DIMM
BDQM4 DQ32~35 10
CLK CS0,CKE CTL Add DQM DQ0~3
D9L
CLK CS1,CKE D9U CTL Add DQM DQ0~3 CLK CS1,CKED10U CTL Add DQM DQ0~3 CLK CS1,CKED11U CTL Add DQM DQ0~3 CLK CS1,CKED12U CTL Add DQM DQ0~3 CLK CS1,CKED13U CTL Add DQM DQ0~3
DQ4~7 10 PCLK2
DQ36~39 10
CLK CS0,CKE D10L CTL Add DQM DQ0~3 CLK CS0,CKE D11L CTL Add DQM DQ0~3 10 CLK CS0,CKE CTL Add DQM DQ0~3 10 CLK CS0,CKE CTL Add DQM DQ0~3 10
BDQM1 DQ8~11 10 PCLK3
BDQM5 DQ40~43
D12L
DQ12~15 10 PCLK4
DQ44~47
D13L
CB0~3 10 BCS3,B3CKE0 BCS2,B1CKE0 PCLK5
CB4~7
BDQM2 DQ16~19 10 PCLK6
CLK CS1,CKE D5L CTL Add DQM DQ0~3 CLK CS1 CTL Add DQM DQ0~3
CLK CS0,CKE D5U CTL Add DQM DQ0~3 CLK CS0,CKE D6U CTL Add DQM DQ0~3 CLK CS0,CKE D7U CTL Add DQM DQ0~3 CLK CS0,CKE D8U CTL Add DQM DQ0~3
BDQM6 DQ48~51 10
CLK CS0,CKE CTL Add DQM DQ0~3 CLK CS0,CKE CTL Add DQM DQ0~3 10 CLK CS0,CKE CTL Add DQM DQ0~3 10 CLK CS0,CKE CTL Add DQM DQ0~3 10 VSS
D14L
CLK CS1,CKED14U CTL Add DQM DQ0~3 CLK CS1,CKE D15U CTL Add DQM DQ0~3 CLK CS1,CKED16U CTL Add DQM DQ0~3 CLK CS1,CKED17U CTL Add DQM DQ0~3
D6L
D15L
DQ20~23 10 PCLK7
DQ52~55
BDQM3 DQ24~27 10 PCLK8 B1RAS,B1CAS,B1WE,B1BA0,B1BA1 B1A0~B1A12 DQ28~31 10
CLK CS1,CKE D7L CTL Add DQM DQ0~3 CLK CS1,CKE D8L CTL Add DQM DQ0~3
D16L
BDQM7 DQ56~59
D17L
DQ60~63
VDD 74ALVCF162835 VDD 10k PCLK9 REGE A11,A12,BA1 74ALVCF162835 CS2,CS3 CKE0 DQM2,3,6,7 LE A0,A1,A2 74ALVCF162835 RAS,CAS,WE CS0,CS1 DQM0,1,4,5 LE OE OE B0A0,B0A1,B0A2 B1A0,B1A1,B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BCS0,BCS1 BDQM0,1,4,5 LE OE B0A11,B0A12.B0BA1 B1A11,B1A12.B1BA1 BCS2,BCS3 B0CKE0,B1CKE0 B2CKE0,B3CKE0 BDQM2,3,6,7 10 CLK0 12pF CLK FBIN
Cb
*1
CLK1,2,3 12pF
G AGND AVDD
A3~A10,BA0
B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0
10
CDCF2510
IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9
PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 PCLK7 PCLK8 PCLK9
FBOUT
Note 1. The actual values of Cb will depend upon the PLL chosen.
Serial PD SCL 47K WP A0 SDA A1 A2
SA0 SA1 SA2
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M390S5658MT1
Preliminary PC133 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2 *1
Control Signal(RAS,CAS,WE) REG
*3 DOUT
*1. Register Input
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RAS CAS WE
*2. Register Output
RAS
td tr td tr
CAS WE
*3. SDRAM
CAS latency(refer to *1) =2CLK+1CLK tSAC tRAC(refer to *1)
1CLK
DQ
tRAC(refer to *2)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CAS latency(refer to *2) =2CLK
tRDL
Row Active
Read Command
Precharge Command
Row Active
Write Command
Precharge Command
td, tr = Delay of register (74ALVCF162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Dont care
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M390S5658MT1
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS
Preliminary PC133 Registered DIMM
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 36 50 Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT1 Min Max 15 15 15 20 15 15 15 22 22 Unit pF pF pF pF pF pF pF pF pF
Parameter Input capacitance (A0 ~ A12) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0) Input capacitance (CLK0) Input capacitance (CS0, CS2) Input capacitance (DQM0 ~ DQM7) Input capacitance (BA0 ~ BA1) Data input/output capacitance (DQ0 ~ DQ63) Data input/output capacitance (CB0 ~ CB7)
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M390S5658MT1
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Burst length =1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = Test Condition
Preliminary PC133 Registered DIMM
Version -75
Unit
Note
Operating current (One bank active) Precharge standby current in power-down mode
ICC1 ICC2P ICC2PS ICC2N
4280 565 185 1430
mA
1
mA
3
Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N Active standby current in non power-down mode ICC3NS
CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0mA Page Burst 4 Banks activated tCCD=2CLK tRC tRC(min) CKE 0.2V
mA 365 710 290 2150 1265 mA mA
3
mA
3
3 3
Operating current (Burst mode) Refresh current Self refresh current
ICC4
4820
mA
1
ICC5 ICC6
7340 605
mA mA
2 3
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 3 Drive ICs. 4. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
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M390S5658MT1
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Preliminary PC133 Registered DIMM
Unit V V ns V
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Notes : Version -75 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
REV. 0.0 Dec. 2001
M390S5658MT1
Preliminary PC133 Registered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3.0 2.5 2.5 1.5 0.8 1 5.4 ns ns ns ns ns ns 3 3 3 3 2 tSAC Symbol Min CLK cycle time tCC 7.5 5.4 ns 2 ns 1,2 -75 Max 1000 ns 1 Unit Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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M390S5658MT1
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS
Preliminary PC133 Registered DIMM
WE DQM BA0,1 A10/AP A12,A11, A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0~A9, A11,A12) Column address (A0~A9, A11,A12)
3 3
Bank active & row addr. Read & column address Write & Column Address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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M390S5658MT1
PACKAGE DIMENSIONS
Preliminary PC133 Registered DIMM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
0.054 (1.372) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)
1.700 (43.18)
(3.000)
0.118
REG
REG
PLL
.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57)
0.250 (6.350) 2.150 (54.61)
0.100 Min
A
B
C
(2.540 Min)
0.700 (17.780)
0.254 Max (6.452 Max)
REG
(3.99 Min)
0.157 Min
0.050 0.0039 (1.270 0.10)
0.250 (6.350)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
(2.540 Min)
0.100 Min
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A Tolerances : 0.005(.13) unless otherwise specified
Detail B
Detail C
SDRAM Part No. : K4S1G0632M - The used device is stacked 256Mx4 SDRAM - Staktek' stacking technology is Samsung' stacking technology of choice s s This module is based on JEDEC PC133 Specification
REV. 0.0 Dec. 2001

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